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74LVX138
LOW VOLTAGE 3 TO 8 LINE DECODER (INV.) WITH 5V TOLERANT INPUTS
s s s
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HIGH SPEED: tPD = 5.5 ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 IMPROVED LATCH-UP IMMUNITY
M1 (Micro Package)
T (TSSOP Package)
ORDER CODES : 74LVX138M 74LVX138T go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. It has better speed performance at 3.3V than 5V LSTTL family combinad with the true CMOS low power consumption. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The LVX138 is a low voltage CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. If the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs will PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1999
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74LVX138
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 2, 3 4, 5 6 15, 14, 13, 12, 11, 10, 9, 7 8 16 SYMBOL A, B, C G2A, G2B G1 Y0 to Y7 NAME AND FUNCT ION Address Inputs Enable Inputs Enable Input Outputs
GND VCC
Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUT S ENABL E G2B G2A G1 C X X L X X H X X H X X X L L H L L L H L L L H L L L H L L L H H L L H H L L H H L L H H
X:Don't Care
OUTPUTS SELECT B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L
LOGIC DIAGRAM
Thislogic diagram has notbe used to esimate propagation delays
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74LVX138
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V mA mA mA mA
o o
ICC or IGND DC VCC or Ground Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top dt/dv Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time (VCC = 3V) (note 2) Parameter Supply Voltage (note 1) Valu e 2 to 3.6 0 to 5.5 0 to VCC -40 to +85 0 to 100 Unit V V V
o
C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V
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74LVX138
DC SPECIFICATIONS
Symb ol Parameter V CC (V) VIH High Level Input Voltage 2.0 3.0 3.6 VIL Low Level Input Voltage 2.0 3.0 3.6 VOH High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current 2.0 3.0 3.0 VOL 2.0 3.0 3.0 II ICC 3.6 3.6 VI = V IH or V IL VI(*) = VIH or VIL
(* )
Test Co nditions Min. 1.5 2.0 2.4 T yp.
Valu e T A = 25 oC Max. -40 to 85 o C Min. 1.5 2.0 2.4 0.5 0.8 0.8 0.5 0.8 0.8 1.9 2.9 2.48 0.0 0.0 0.1 0.1 0.36 0.1 2 0.1 0.1 0.44 1 20 Max.
Un it
V
V
I O =-50 A IO=-50 A IO=-4 mA IO=50 A IO=50 A IO=4 mA
1.9 2.9 2.58
2.0 3.0
V
V A A
VI = 5V or GND VI = VCC or GND
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol Parameter V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 3.3 -0.5 3.3 3.3 C L = 50 pF 0.8 Test Co nditions
o
Valu e T A = 25 C Min. T yp. 0.3 -0.3 2 Max. 0.5 -40 to 85 C Min. Max.
o
Un it
V
1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz
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74LVX138
AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns)
Symb ol Parameter V CC (V) tPLH tPHL Propagation Delay Time A, B, C to Y 2.7 2.7 3.3(*) 3.3(*) 2.7 2.7 3.3 3.3(*) tPLH tPHL Propagation Delay Time G2A or G2B to Y 2.7 2.7 3.3(*) 3.3(*) 2.7 3.3
(*) (*)
T est Con ditio n CL (p F) 15 50 15 50 15 50 15 50 15 50 15 50 50 50
Valu e T A = 25 oC -40 to 85 o C Min. T yp. Max. Min. Max. 7.1 13.8 1.0 16.5 9.6 5.5 8.0 8.7 11.2 6.8 9.3 8.8 11.3 6.9 9.4 0.5 0.5 17.3 8.8 12.3 16.3 19.8 10.6 14.1 16.0 19.5 10.4 13.9 2.5 2.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 20.0 10.5 14.0 19.5 23.0 12.5 16.0 18.5 22.0 11.5 15.0 2.5 2.5
Un it
ns
tPLH tPHL
Propagation Delay Time G1 to Y
ns
ns
tOSLZ tOSHL
Output to Output Skew Time (note 1, 2)
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V 0.3V
CAPACITIVE CHARACTERISTICS
Symb ol Parameter V CC (V) C IN CPD Input Capacitance Power Dissipation Capacitance (note 1) 3.3 3.3 fIN = 10 MHz Test Co nditions
o
Valu e T A = 25 C Min. T yp. 4 34 Max. -40 to 85 C Min. Max.
o
Un it
pF pF
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC
TEST CIRCUIT
CL = 50 pF or equivalent (includes jigand probe capacitance) RT = ZOUT of pulse generator (typically 50)
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74LVX138
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; duty cycle 50%)
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; duty cycle 50%)
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74LVX138
SO-16 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
7/9
74LVX138
TSSOP16 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 4.9 6.25 4.3 5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.20 5.1 6.5 4.48 0.002 0.335 0.0075 0.0035 0.193 0.246 0.169 0.197 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.201 0.256 0.176
DIM.
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
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74LVX138
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com .
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